1. Field of the Invention
The present invention relates to the field of semiconductor laser driver circuits.
2. Prior Art
Existing high speed laser driver integrated circuits require a single power supply of approximately 5 V, or multiple power supplies. However, electronics systems are evolving toward lower supply voltages to conserve power and to exploit improving low voltage, high frequency IC processes. Therefore, it is an objective to provide a laser driver circuit capable of operating with a single supply voltage as low as 3 V. It is also an objective to provide operation with existing 5 V systems.
It is also an objective of the invention to comply with existing SDH/SONET specifications at 2.448 Gb/s, or faster.
It is also an objective of the invention to minimize power consumption.
It is also an objective of the invention to provide a wide range of laser modulation current (such as 5 mA to 60 mA) while meeting the previous objectives.
It is a further objective of the invention to be directly compatible with standard PECL logic at the data inputs.
FIG. 1 is a simplified schematic of a typical (Maxim MAX3261, Sony CXB1108AQ) integrated bipolar laser driver. The output transistors Q1 and Q2 switch the modulation current Imod into an external laser depending on the state of the differential data inputs Vin+, Vin-. RL represents the typical matching impedance of a high speed laser (e.g., 25 .OMEGA.). Emitter follower transistors Q3 and Q4 provide level shifting and current gain to drive the output transistors. Additional emitter followers can be included for more level shifting and current gain ("A Versatile Si-Bipolar Driver Circuit with High Output Voltage Swing for External and Direct Laser Modulation in 10 Gb/s Optical-Fiber Links", H.-M. Rein et al., IEEE Journal of Solid-State Circuits, Vol. 29, No. 9, September 1994). Differential pair Q5 and Q6 provides voltage gain to ensure full switching of the output devices by switching current I3 through R1 or R2 depending on the input data. The inputs can be buffered by optional emitter followers (not shown).
The circuit of FIG. 1 directly couples the output current from the collector of transistor Q1 to the laser. Since the supply voltage must be greater than the headroom needed by the current source Imod, plus the output transistor Q1, plus the laser, this topology is not capable of operation with a supply voltage of 3 V. For example, transistor Q1 and current source Imod both need about 1 V of headroom for high speed operation, the typical DC laser drop is 1.5 V, and a modulation current of 60 mA multiplied by the 25 .OMEGA.of RL is 1.5 V. This is a total of 5 V, which clearly shows that operation on a single 3 V DC supply is not possible.
The circuit of FIG. 2 can be used to AC couple the output current from the collector of transistor Q1 to a semiconductor laser. By using an inductor to set the DC voltage at the collector of Q1 to be equal to the supply, adequate headroom is achieved. The value of the inductor LAC is chosen to limit droop during long consecutive streams of data ones or zeros and the value of the capacitor CAC is chosen to provide the desired high pass cutoff frequency. The use of this output topology allows sufficient headroom for 3 V operation. This topology is commonly used in RF applications, and it has been previously applied to semiconductor lasers. Similar AC coupling networks with resistive pull-up have been previously implemented.
A disadvantage of the circuit of FIG. 1 is that the emitter follower currents I1 and I2 must be approximately equal to the peak base current (caused by collector to base capacitance) of the output transistors Q1 and Q2. At high data rates and with large modulation current, I1 and I2 can become very large (10's of mA). Transistors Q3 and Q4 must therefore be large devices and will also have significant transient base current. This sets a maximum value for R1 and R2 and can cause the value of current I3 to be larger than desired. The value of current I3 multiplied by R1 (or R2) results in the peak magnitude of the differential voltage signal across the bases of transistors Q1 and Q2. This signal must be large enough to fully switch the modulation current at its maximum value. The required amplitude is typically 400 mV for 60 mA of modulation current.